A known process for forming short channel (SC) and long channel (LC) devices on a 14 nm FinFET device results in a 28 nm gate height (GH) for both devices post metal gate chemical mechanical polishing (CMP). The resulting margin between the SC fin top work function (WF) metals and gate surface, e.g., 14 nm to 15 nm, is much greater than the margin for the LC devices. It is desirable to reduce the SC GH or margin to reduce the effective capacitance (Ceff) of the device and, therefore, improve the ring oscillator (RO) performance of the device. However, the LC devices on the FinFET device cannot be further polished without the risk of exposing the LC fin top WF metals due to an extremely limited LC margin and a common CMP dishing issue on long and wide gate areas.
A need therefore exists for methodology enabling a reduction of the SC GH on a FinFET device without exposing the fins of the LC devices and the resulting device.